absolute maximum ratings (ta = 25?) applied voltage power dissipation storage temperature operating temperature input voltage pd * 1 reduced by 3.0mw for each increase in ta of 1 c over 25 c. v cc parameter symbol tstg topr ?0.3 ~ + 7.0 limits ?65 ~ + 125 ?40 ~ + 85 ?0.3 ~ v cc + 0.3 mw v unit c c v 300 * applications 168-pin and 144-pin dram modules containing syn- chronous dram features 1) 2-k bit eeprom with configuration of 256 words 8 bits. 2) compliance with spd data format. 3) dual-line serial (i 2 c bus) interface. 4) protective functions enabled by a one-time rom and write protect pin. soft ware protection. as a one-time rom: 00 to 7fh. hard ware protection (wp pin): 80 to ffh. 5) compact ssop-b 8-pin package. 1 memory ics serial interface ic for dimms sup- porting plug & play BU9877FV the BU9877FV is a 2-k bit eeprom with a write protect function, developed for dimms (dual in-line memory modules) containing a synchronous dram. this ic stores ids in memory in order to enable plug & play functions. recommended operating conditions (ta = 25?) power supply voltage input voltage v in v cc parameter symbol v v unit 2.7 ~ 5.5 limits 0 ~ v cc
2 memory ics BU9877FV block diagram 1 2 3 4 8 vcc a0 a1 a2 gnd wp scl sda 7 6 5 2048bit eeprom array 8bit 8bit 8bit address decoder slave ?word address register data register start stop control circuit write protect control circuit ack high voltage generator power supply voltage detector pin descriptions note: the sda pin is nch open drain output, and should be used with external pull-up resistor. the wp pin is equipped with internal pull-down resistor, so can be left open when used. slave address setting (pin) input / output reference voltage of 0v slave and word address, serial data input / output serial clock input write protect input connect the power supply to this. pin name pin no. function i / o a0, a1, a2 1, 2, 3 i gnd 4 sda 5 i / o scl 6i wp 7i v cc 8 electrical characteristics (unless otherwise noted, ta = ?40 to + 85?, vcc = 2.7v to 5.5v) v ih input high level voltage v v il input low level voltage 0.3v cc v v ol output low level voltage i ol = 3.0ma (sda) fig.1 0.4 v i li1 input leakage current 1 v in = 0v ~ v cc fig.2 1 m a i li2 input leakage current 2 v in = 0v ~ v cc (wp) fig.2 20 m a i lo output leakage current v out = 0v ~ v cc fig.2 1 m a i cc operating current consumption v cc = 5.5v, f scl = 100khz fig.3 3.0 ma i sb standby current v cc = 5.5v, sda ?scl = v cc fig.4 2.0 m a f scl scl frequency 100 khz parameter symbol measurement circuit 0.7v cc ?1 ?1 ?1 min. typ. max. unit conditions
3 memory ics BU9877FV measurement circuits v cc v cc v ol data set when output is low 3.0ma gnd v sda fig. 1 low output voltage measurement circuit v cc v out = 0 ~ v cc v in = 0 ~ v cc i lo i li v cc gnd a a0, a1, a2 sda, scl, wp fig. 2 input / output leakage current measurement circuit v cc i cc v cc v cc gnd a sda wp scl 100khz clock write / read input a0, a1, a2 fig. 3 current consumption measurement circuit v cc v cc i sb v cc gnd a sda wp scl a0, a1, a2 fig. 4 standby current measurement circuit
4 memory ics BU9877FV circuit operation (1) synchronous data i / o timing scl sda (input) sda (output) t r t hd: sta t hd: dat t su: dat t f t low t buf t pd t dh t high scl sda t su: sta t su: sto t hd: sta start bit stop bit fig. 5 ?reading of input is done at the rising edge of scl. ?output of data is synchronized to the falling edge of scl.
5 memory ics BU9877FV operation timing characteristics (unless otherwise noted, ta = ?40 to + 85? , vcc = 2.7v to 5.5v) parameter symbol typ. max. min. unit data clock high time t high 4.0 m s t su: sta start condition setup time 4.7 m s t pd 3.5 output data delay time m s t dh 0.3 output data hold time m s t su:sto 4.7 stop condition setup time m s t buf 4.7 bus release time prior to start of transfer m s t i 0.1 effective noise elimination interval (scl, sda pins) m s t hd: sta start condition hold time 4.0 m s t f 0.3 sda / scl fall time m s t r sda / scl rise time 1.0 m s t low data clock low time 4.7 m s t hd: dat input data hold time 0 ns t su: dat input data setup time 250 ns t wr1 10 ms t wr2 15 ms internal write cycle time * 1 * 2 * 1 v cc = 4.5v to 5.5v * 2 v cc = 2.7v to 5.5v (3) start condition (start bit recognition) before executing the various commands, a start condi- tion (start bit) must be input. this is recognized when scl is high and sda falls from high to low. if a start condition is not input, no commands will be received. (4) stop condition (stop bit recognition) to terminate the various commands, a stop condition (stop bit) must be input. this is recognized when scl is high and sda rises from low to high. (5) precautions concerning the write command with the write command, internal writing is initiated by inputting the stop bit after the data has been input. (6) device addressing (specifying the slave address) the master address should be output first, followed by the start condition, and then the slave address. the first four bits of the slave address are used to recog- nize the device type. the device code for this ic is fixed at "1010". when accessing the write protect regis- ter, a device code of "0110" is used. the next three bits of the slave address (a2, a1, a0) are used to select the device, and the ic begins to function only if the data input for a2 to a0 matches the states of input pins a2 to a0. consequently, up to eight of these ics may be connected on the same bus, depending on the combination of a2 to a0. the last bit of the slave address (r / w) is used to specify either writing or reading, and is as shown below. r / w set to 0: writing or random read r / w set to 1: reading device type device address access to write protect register access to memory a2 a2 a0 a0 a1 a1 0110 1010 r / w w
scl (from master) sda (master output data) sda (data output from the BU9877FV) acknowledge signal (ack signal) start condition t pd fig. 6 acknowledge signal (ack signal) response (when slave address is input for writing or reading) 189 6 memory ics BU9877FV (7) write protect command the write protect command is used to prohibit writing of data to addresses 00 to 7fh, among the 256 word address data. be aware that once a write protect regis- ter has been specified, it cannot be canceled (one-time memory). the write protect command can function regardless of the state of the wp pin. (8) wp (write protect pin) setting the wp pin to vcc (high level) has the same effect as using the write protect command, and inhibits writing of data to addresses 80 to ffh, among the 256 word address data. normal writing is enabled by set- ting this pin to gnd (low level). (if the write protect command is used to inhibit writing, data cannot be writ- ten regardless of the status of the wp pin.) the wp pin is equipped with an internal pull-down resistor, so if the protect function is not being used, this should be left open or set to gnd. (9) ack signal the acknowledge signal (ack signal) is determined by the software, and indicates whether or not the data has been correctly transmitted. regardless of whether the address is a master or slave address, the device on the transmitter (sending signal) side (the master when a slave address is input for a write command or a read command, and the eeprom when read command data is output) opens the bus after this 8-bit data is out- put. with a device on the receiving (reception) side (the eeprom when a slave address is input for a read command or write command, and the master when data is output for a read command), sda is set to low during the nine-clock cycle, and the acknowledge sig- nal (ack signal) is output when 8-bit data is received. for writing operations, the acknowledge signal (ack signal) is output in the low state each time that 8-bit data (word address or write data) is received. in reading operations, 8-bit data (read data) is output, and then the acknowledge signal (ack signal) in the low state is detected. if the acknowledge signal (ack signal) is detected and no stop condition is sent from the master (microcomputer) side, this ic continues to output data. if the acknowledge signal (ack signal) is not detected, this ic interrupts the transmission of data, recognizes a stop condition (stop bit), and terminates the reading operation. the ic then enters the standby mode.
7 memory ics BU9877FV (10) timing charts scl start condition stop condition sda 11 00 slave address word address write data ack signal (output) a2 a1 a0 0 wa7 wa6 wa0 d7 d0 18917182627 fig. 7 byte write cycle ?data is written to the address specified by the word address (n address). ?after 8 bits of data are input, a stop bit is generated. this initiates writing of the data to the memory cell. fig. 8 current read cycle scl start condition stop condition sda 1 1 00 slave address read data ack signal (output) ack signal (input) a2 a1 a0 1 d7 d6 d5 d2 d1 d0 1 1 8 918 ?this ic has an internal circuit address counter to store the previously accessed address in the memory. if the pre- vious command was a write command, the write word address data (n) is read, and if the previous command was a read command, the read word address data (n) incremented by one address (n + 1) is read. ?if the ack signal low following d0 is detected and no stop condition is sent from the master side, reading can be continued sequentially to the next data.
8 memory ics BU9877FV scl start condition start condition stop condition sda 10 0 0 slave address word address slave address read data ack signal (output) ack signal (input) a2 a1 a0 wa7 wa0 10 0a2a1a0 1 11 d7 d0 1 fig. 9 random read cycle ?this command enables reading of the data at the specified word address. ?if the ack signal low following d0 is detected and no stop condition is sent from the master side, reading can be continued sequentially to the data of the next word address. ?to terminate this command, high is input at the ack signal timing (following any d0), then stop condition is input. slave address read data read data ack signal (output) ack signal (input) scl start condition stop condition sda 11 1 00 a2 a1 a0 d7 d7 d0 d0 n + a fig. 10 sequential read cycle ?if the ack signal is detected following d0 and no stop condition is sent from the master side, reading can be con- tinued sequentially to the data of the next word address. ?to terminate this command, high is input at the ack signal timing (following any d0), then stop condition is input.
?the write protect command is used to prohibit writing of data to addresses 00 to 7fh, among the 256 word address data, and cannot be altered (one-time memory). ?the command is canceled if a stop condition has been input before the 27th clocks. ?if the write protect command is input when the protect status is already in effect, the command is canceled. external dimensions (units: mm) 0.1 0.22 0.1 0.65 0.3min. 5 4 8 1 6.4 0.3 4.4 0.2 3.0 0.2 1.15 0.1 0.15 0.1 0.1 (0.52) ssop-b8 9 memory ics BU9877FV scl start condition stop condition sda 11 00 slave address word address write data ack signal (output) a2 a1 a0 0 don't care don't care 18917182627 fig. 11 write protect cycle
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